The scan-based self-test technique (scan-based BIST) is a design technique for enhanced testability of synchronous circuits, which combines the traditional built-in self-test technique with the scan design technique to enhance the test effectiveness of digital systems. In the built-in self-test technique, a pseudo-random test pattern generator and a test response compressing logic are embedded into the circuit, where a phase shifter (PS) is also added to reduce the interdependence test signals generated by separate stages of the pseudo-random test pattern generator. The new invention is an effective means to reduce testing time and testing cost of the chips. The scan design makes flip-flops in the circuit controllable and observable and connects these scan flip-flops to form one or more scan chains. Once a fill scan method is used, test pattern generation of the synchronous sequential circuit becomes test pattern generation of the combinational circuit, thus cost of test pattern generation can be reduced greatly, and complete fault coverage can be achieved. The scan design is, therefore, the most popular testability design method used in the field.
Scan-based self-test is usually classified into two classes: test-per-clock BIST and test-per-scan BIST. In the test-per-clock mode, application of a test vector and test response compression are completed in one clock, and testing time required by such self-test structure is relatively short, but hardware overhead required to implement it is very high; as for the test-per-scan BIST, a test vector under is applied into the scan chains through the phase shifter (all scan flip-flops in a scan chain is controlled by the same scan enable signals, wherein it is 1 during the scan shift mode, and 0 for the capture cycle for all scan flip-flops to receive test responses). The circuit is turned to the functional mode after a test vector has been shifted into the scan chain while the test vector corresponding to the primary inputs is applied to the circuit, test responses are captured by the scan flip-flops and received at the primary outputs by the multiple input signature analyzer (MISR). Then the circuit turns to the test mode again; the response information in the scan chain is shifted out to a multi-input signature analyzer (MISR), while next test vector is applied into the scan chain. The hardware overhead of such self-test structure can be reduced, but the test time required increases linearly corresponding to the length of the scan chain. FIG. 1 shows a block diagram of the architecture of the test-per-scan self-test technique.
As shown in FIG. 1, a linear feedback shift register (LFSR) and a phase shifter (PS) are used to generate pseudo-random test vectors, SC is a scan chain, which is constructed by connecting scan flip-flops in the circuit. CP represents control points, and OP represents observation points. The function of the multiple input signature analyzer (MISR) is to collect and compress the test responses. The outputs of the pseudo-random test generator (LFSR) connects with the phase shifter (PS), where outputs of the phase shifter drives the scan chains and primary inputs of the circuit. And finally the test responses are collected and compressed by the multi-input signature analyzer.
In the test-per-scan mode, a scan cycle refers to the clock cycles to apply a test vector into (or shifting out the test responses from) a scan chain, during which the circuit is in the test state. A capture cycle refers to the time required for collecting test responses, during which the circuit is set to the normal operation state. One test period comprises one scan period and one capture period. Generally, for a signal line l, the i controllability Ci(l) (i∈{0,1} is defined as the probability that value i is assigned to a signal line l by a randomly selected input vector; and the observability O(1) is defined as the probability for the value on the signal line l to be propagated to a primary output or the scan output by randomly selecting an input vector.
The duration of random self-test is closely relevant to the number of hard-to-test faults. Many techniques have been proposed to solve this problem: (1) weighted random testing, (2) test points insertion, (3) improved pseudo-random test pattern generators, and (4) new scan architecture.
Traditional weighted random test refers to applying weighted random signal having different signal probabilities (probabilities of the value of signal being 1) as the test vector, to reduce the time required for achieving a predetermined fault coverage. Many research results have been achieved on this technique. Bardell, Mc Anney and Savir have proposed a backtracing algorithm for calculating the weights of the primary inputs and outputs of the circuit. Calculation of this method is very simple. Pomeranz and Reddy proposed a method for generating weighted random test pattern, which can increase fault coverage. Recently, Tsai, Cheng and Bhawmilk introduced a scan-based BIST method with multiple capture cycles for each test cycle, which can improve the test effectiveness effectively.